Technical Field
Embodiments of the present disclosure relate to semiconductor memory devices and data processing systems and, more particularly, to a method for repairing defective memory cells of a semiconductor memory device.
Discussion of Related Art
A data processing system including a processor may use a main memory such as a dynamic random access memory (DRAM) as a working memory.
A DRAM module including a plurality of DRAMs is controlled by a memory controller that receives a request from a processor to perform a memory control operation.
A DRAM may include a memory cell that includes a single access transistor and a single storage capacitor. When it is difficult to properly retain data stored in a certain memory cell, the memory cell may become a defective memory cell. The defective memory cell refers to a memory cell that causes a read error irrespective of hard failure or soft failure.
A defective memory cell hard-failed during manufacturing of a DRAM is typically repaired using a spare memory cell in a redundancy memory area. Repair units may include various units such as cell-to-cell, row-to-row, column-to-column, and block-to-block.
After shipment of a dynamic random access memory (DRAM) and during its operation, a weak memory cell may lose its stored data before a refresh period arrives. A memory cell failed during the operation of the DRAM may result in a read error, i.e., stored data cannot be read normally.
Although an ECC engine may be adapted in a memory controller to correct a read error, there is a limitation in correction using the ECC engine. Accordingly, there is a need for effectively repairing a defective memory cell causing a read error continuously or frequently on a board during the operation of a data processing system.